1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a structure of a semiconductor device and method of fabricating the same. Although the present invention is suitable for a wide range of applications, it is particularly suitable for a highly integrated transistor.
2. Discussion of the Related Art
A conventional structure of a semiconductor device and method of fabricating the same will be explained with reference to the attached drawings.
FIG. 1 is a cross-sectional view of a conventional structure of a semiconductor device. A field oxide layer 15 is formed at a field region of a semiconductor substrate 11 defined as an active region and a field region. A gate insulating layer 16 is formed on a predetermined portion of the active region and a gate electrode 19 is formed on the gate insulating layer 16. Sidewall spacers 21 are formed on both sides of the gate insulating layer 16 and the gate electrode 19, and a source/drain impurity diffusion region 22 having a LDD (lightly doped drain) structure is formed in the substrate 11 on each side of the gate electrode 19 adjacent to the sidewall spacers 21.
FIGS. 2A-2E are cross-sectional views showing a conventional method of fabricating a semiconductor device having the aforementioned structure. First, an initial oxide layer 12 is formed in order to release stress imposed on an interface of a semiconductor substrate and a nitride layer 13 is deposited on the entire surface of the initial oxide layer 12, as shown in FIG. 2A.
Subsequently, a first photo resist layer 14, as shown in FIG. 2B, is coated on the nitride layer 13 and then is patterned by an exposure and development process. Using the patterned first photo resist layer 14 as a mask, the nitride layer 13 is partially removed to define a field region and an active region. A region where the nitride layer 13 has been removed is defined as a field region, whereas a region below the remaining nitride layer 13 is defined as an active region. Using the first photo resist layer 14 as a mask, ions are implanted into the field region to increase the insulation characteristic of the field region. In this process, by increasing the concentration of the implanted ions, the value of the threshold voltage can be increased.
Referring to FIG. 2C, the first photo resist layer 14 used as a mask for ion implantation is removed. Using the nitride layer 13 as a mask, an oxidation process is carried out to form a field oxide layer 15 in the field region. The nitride layer 13 and the initial oxide layer 12 are removed. A gate insulating layer 16 is formed on the surface of the substrate 11 between the field oxide layers 15 and then a polysilicon layer 17 for a gate electrode is formed on the entire surface of the gate insulating layer 16. Thereafter, a second photo resist layer 18 is provided on the polysilicon layer 17 and patterned by an exposure and development process.
Referring to FIG. 2D, using the second photo resist layer 18 as a mask, the polysilicon layer 17 and the gate insulating layer 16 are partially removed so that a gate electrode 19 is formed. Using the gate electrode 19 as a mask, impurity ions are lightly implanted into the entire surface of the substrate 11 to form a lightly doped impurity regions 20 in the substrate 11.
Finally, as shown in FIG. 2E, an insulating layer (not shown) is deposited on the entire surface including the gate electrode 19 and is subjected to etch back to form sidewall spacers 21 on both sides of the gate insulating layer 16 and the gate electrode 19. After forming the sidewall spacers 21, impurity ions are heavily implanted into the substrate 11 using the gate electrode 19 and the sidewall spacers 21 as masks to form a source/drain impurity region 22 having a LDD structure.
Nevertheless, a conventional structure of a semiconductor device and method of fabricating the same has the following problems.
Since a field oxide layer used as an isolation region for isolating devices occupies a large area, it is not feasible for fabricating highly integrated devices.